Abstract

Compilers for Low Power

In our talk, we will summarize recent research efforts in reducing power dissipations from compilers and system software for both dynamic power and static powers. We will also present our research work in the areas. This will include dynamic power reduction for instruction bus for VLIW architectures, power-gating controls for reducing static powers, and multiple domain assignments for power controls with embedded systems. In the aspect of power gating control, a Sink-N-Hoist framework in the compiler solution is proposed to generate balanced scheduling of power-gating instructions. In addition, we will also introduce our previous experience with low-power scheduling on a MOEA project for scalable security processors. We propose a novel heuristic that integrates the utilization of DVS and PG and increases the total energy reductions. An analytical model approach is introduced for assigning voltage domains for multiple voltage domains in SoC environments. We will also report our experimental results with these techniques. A part of our work presented in the talk will be based on a series of our low-power papers in ISSS 2000, LCPC 2002, ACM TODAES 2003, LCPC 2004, EMSOFT 2005, and a work to appear in ACM TODAES.

Low Power Techniques for Video Subsystem

In battery-powered electronic devices such as laptop computers and digital cameras, typically the video subsystem consumes most of the system power. In our talk, we will focus on TFT-LCD monitors, the most popular displays for portable systems nowadays, and review low-power techniques for reducing their power consumption.

Real-Time Energy-Efficient Task Scheduling and System Design Issues

In this talk, I will address several energy-efficient system design issues for operating systems and application systems. In particular, I will summarize our work on flash-memory storage systems, real-time kernels, sensor-node power assignment, and energy-profiling. This talk will also cover parts of our work on task scheduling with energy consumption and response time constraints. In particular, I will cover several task models and their scheduling/approximation algorithms for energy-efficient task scheduling.

Power-Aware Architecture Design

In this talk, I will introduce the state-of-art techniques of the power-aware architecture design. Topics include adaptive architecture, system power management, architectural power/thermal models, and power/thermal issues in SMT and multi-core processors. I will also go over some of my latest research results, including energy-efficient cache/flash storage design, and a thermal-aware architectural floorplanning framework.

DVFS Architecture and Its Implementation

Traditional low-power design technologies, such as clock gating, frequency scaling, has been used for years to achieve power savings in an MPU-based SoC. Recently, the combination of voltage scaling and frequency scaling was employed to further reduce the power consumption in power-critical components. ITRI has used the concept of just-in-time computing coupled with dynamic voltage scaling (DVFS) to develop the PAC-LP application-aware power management solution package and employ it in a dual-core SoC Platform PAC (Parallel Architecture Core). This talk will introduce the basic concept of DVFS SoC design technology basic concept and its implementation. DVFS design flow, Multi-VDD standard cell library, level shifter, and some related future works are also elaborated in this talk.

Toggle Finder: An Accurate and Fast RTL Power Estimator for Large Designs

Power estimation at the Register Transfer Level (RTL) often suffers from inadequate accuracy when applied to large designs.We address this issue by a multi-mode estimation methodology with two major techniques. Firstly, we use a power mode classification scheme to refine the power-consuming behaviors of a large design.Secondly, we incorporate a functional weighting scheme for easy power characterization. The combination of these two techniques jointly contributes to higher accuracy. The proposed methodology has been realized as a practical tool that can fit into the commercial design flow. Experimental results of an in-house large design with 132K gates and other smaller ones show that the estimation error can be reduced down to only 3 % for typical functional patterns.

Energy-efficient On-chip Communication Architecture Synthesis

To reduce design complexity, an SOC is typically designed as a network of IP cores including embedded processors, dedicated functional blocks, and memories, etc. A robust SOC design methodology includes two major tasks: (1) HW/SW partitioning of a system, and mapping computation requirements of the system to a set of IP cores, and (2) mapping communication requirements among IP cores to a well designed communication architecture. Increasing level of integration due to process advancement and IP reuse creates numerous intra-synchronous components with decreasing level of functional granularity, and growing volume and diversity of communication demands among IP cores. This trend makes the design of on-chip communication architectures become much more important, and corresponding design methodology and tools should be included in any system design flow.

In this talk, we will present our recent results in on-chip communication architecture synthesis. Both shared bus and point-to-point schemes will be discussed. The goal of our approaches is to efficiently and effectively explore design space such that the resultant communication architecture has communication energy as small as possible while satisfying given performance constraints. Our approaches also include communication-driven floorplanners to perturb and capture the location and shape of each IP. Experimental results will be shown to support our approaches.

About the Speakers

Prof. Jenq Kuen Lee

JENQ-KUEN LEE received the B.S. degree in computer science from National Taiwan University in 1984. He received a Ph.D. in computer science from Indiana University in 1992, where he also received a M.S. (1991) in computer science. He was a key member of the team who developed the first version of the pC++ language and SIGMA system while at Indiana University. He joined the Department of Computer Science at National Tsing-Hua University, Taiwan, in 1992. Since then, he established a programming language research lab. there to develop advanced system toolkits for high-performance and embedded systems. He is now a professor with the computer science department, National Tsing-Hua Univ., Taiwan. He was a recipient of the most original paper award in ICPP '97 with the paper entitled "Data Distribution Analysis and Optimization for Pointer-Based Distributed Programs". The dissertation of his Ph.D. student, Gwan-hwan Hwang, also received the distinguished dissertation award as honorable mention by IICM of Taiwan, 1999. He was also a recipient for a Taiwan MOE award, 2001, on delivering system software technologies for advancing the related industry sector in Taiwan. He was also a recipient of Microsoft Research Award for Embedded Systems, Redmond, 2003.

He currently led a MOEA research project (2005-2008) with 9 faculties to develop system toolkits and architecture designs for high-performance and low-power dual-core processors. His research interests include optimizing compilers, computer architectures, distributed component software technologies, and low-power technologies.

Also see http://www.cs.nthu.edu.tw/~jklee.

Prof. Wei-Chung Cheng

Wei-Chung Cheng received his B.S. degree in Mechanical Engineering and Computer Engineering from the National Chiao-Tung University, M.S. degree in Computer Science from the National Tsing-Hua University, and Ph.D. degree in Electrical Engineering from the University of Southern California. His doctoral research focused on power-aware computer systems, particularly in the areas of low-power bus encoding, low-power video interface, and low-power video subsystem. Currently he is an Assistant Professor at the Department of Photonics, National Chiao-Tung University, where he established the Perception Oriented Design Lab (PODLAB, http://color.eic.nctu.edu.tw) dedicated to perception-oriented, power-aware driving techniques for portable flat panel displays.

Prof. Tei-Wei Kuo

Prof. Tei-Wei Kuo received the B.S.E. degree in Computer Science and Information Engineering from National Taiwan University in Taipei, Taiwan, in 1986. He received the M.S. and Ph.D. degrees in Computer Sciences from the University of Texas at Austin in 1990 and 1994, respectively. He is currently a Professor at the Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan, ROC. His research interests include embedded systems, real-time operating systems, real-time database systems, and information servers.

Dr. Kuo serves as an Associate Editor of the Journal of Real-Time Systems (SCI) since 1998 and is in the editorial board of the Journal of Information Science and Engineering (EI) since 2005 and the Journal of Embedded Computing since 2004. Prof. Kuo a program committee member of many international conferences around the world. He is a Program Chair of the Seventh International Conference on Real-Time Computing Systems and Applications (RTCSA 2000), Cheju Island, Korea, December 12-14, 2000, a Program Chair of the IEEE Real-Time Technology and Applications Symposium, Taipei, Taiwan, in 2001, and the Program Chair for Asia and Far East of the Ninth International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS 2001) in San Francisco, USA, in 2001. Starting from 2003, he served as a member of the steering committee of IEEE RTCSA. He is now an executive committee member of the IEEE Technical Committee on Real-Time Systems and the steering committee chair of IEEE RTCSA.

Dr. Kuo received several research awards in Taiwan, including the Distinguished Research Award from the ROC National Science Council in 2003 and the Young Scholar Research Award from Academia Sinica, Taiwan, ROC, in 2001. He has over 100 technical papers published or been accepted in international journals and conferences and has a book "Real-Time Database Systems: Architecture and Techniques" published by Kluwer Academic Publishers (ISBN 0-7923-7218-2, USA).

Prof. Chia-Lin Yang

Chia-Lin Yang received the B.S. degree from the National Taiwan Normal University in 1989, and the M.S. degree from the University of Texas at Austin in 1992. In 1993, she joined VLSI Technology Inc.(now Philips Semiconductors) as a software engineer. In 2001, she received the Ph. D degree from the Department of Computer Science at Duke University. She is currently an Associate Professor at the Department of Computer Science and Information Engineering, National Taiwan University. Her research interests include energy-efficient microarchitectures, memory hierarchy design, and multimedia workload characterization. Yang is the recipient of a 2000-2001 Intel Foundation Graduate Fellowship Award and she is a member of the ACM and IEEE.

Wen-Feng Chen -- Dept. Manager, IP Technology Dept., STC/ITRI

Wen-Feng Chen serves as the Dept. Manager of IP Technology Dept. in STC/ITRI, who is responsible for the planning, evaluation, and outsourcing of IP in ITRI. He is currently leading the dual-core SoC project (PAC SoC Platform) in STC/ITRI. Wen-Feng has more than 10-year experience in computer architecture, platform-based design, multi-processor system design, and microprocessor design including the first RISC MPU project in ITRI.
Wen-Feng received Master degree in Applied Mathematics from National Chung-Hsing University in 1985. He serves as the chairman of technical WG in IP Qualification Alliance (IPQA) and Reviewer of SIP Design Contest hosted by Ministry of Education. His current research interests include computer architecture design, low-power SoC design, and system performance evaluation.

Prof. Shi-Yu Huang

Shi-Yu Huang received his BS, MS degrees in Electrical Engineering from National Taiwan University in 1988, 1992 and Ph.D. degree in Electrical and Computer Engineering from the University of California, Santa Barbara in 1997, respectively. From 1997 to 1998 he was a software engineer at National Semiconductor Corp., Santa Clara, investigating the System-On-Chip design methodology. From 1998 to 1999, he was with Worldwide Semiconductor Manufacturing Corp., designing the high-speed Built-In Self-Test circuits for memories. He joined the faculty of National Tsing-Hua University, Taiwan, in 1999, where he is currently an Associate Professor. Dr. Huang’s research interests are mainly in design automation for VLSI, with an emphasis on formal verification, power estimation and fault diagnosis. He ever co-authored a book entitled "Formal Equivalence Checking and Design Debugging" published by Kluwer Academic Publishers in 1998.

黃錫瑜博士分別在1988年及1992 年取得台灣大學電機系的學士學位及碩士學位， 1997 年獲得美國『加州大學聖塔巴巴拉分校』的電機與計算機工程博士學位。從1999年起，在台灣清華大學電機系任教至今，目前為副教授。黃博士曾在美國 National Semiconductor 及台灣的世大積體電路公司 (後為台積電併購) 服務，從事有關系統晶片驗證及記憶體自我測試電路的設計工作。他目前的主要研究領域是積體電路設計與設計自動化，包括CMOS影像感測器設計 , 低功率記憶體電路設計 , 功率估算軟體 ，邏輯晶片瑕疵診斷軟體等等。

Prof. Ting-Chi Wang

Ting-Chi Wang received the B.S. degree in Computer Science and Information Engineering from National Taiwan University, and the M.S. and Ph.D. degrees in Computer Sciences from the University of Texas at Austin. He is currently an Associate Professor in the Department of Computer Science, National Tsing Hua University. Prior to joining National Tsing Hua University, he was with Texas A&M University and Chung Yuan Christian University as a faculty member. His research interests include physical design, on-chip communication architecture synthesis, and IP verification.